IBM Power 10 CPU
The POWER10 processor by model: cores per socket, clock ranges, eSCM and DCM packaging, the IBM i software tier each configuration lands in, and how to read the CPU out of an installed Power 10.
POWER10 is the processor most IBM i and AIX shops are either running now or comparing against. It is the generation that introduced on-chip matrix math acceleration, moved memory onto the Open Memory Interface, and brought PCIe Gen5 to the platform. This page sets out which CPU options each Power 10 model shipped with, what those choices do to your IBM i software tier, and how to confirm what is physically in a machine you already own.
Three POWER10 changes matter more than the clock speed. The Matrix Math Accelerator put inferencing on the core itself, so AI scoring runs inside a database transaction without a separate accelerator. The Open Memory Interface decoupled memory from the processor's pin budget, which is how a two-socket S1024 reaches 8 TB. And transparent memory encryption became a platform feature rather than a workload cost. Those are the reasons a Power 10 core does more real work than its frequency suggests.
Power 10 CPU options by model
POWER10 processor options, cores and clock ranges by model
| Model | Sockets | Cores per socket | Typical clock range (GHz) | System maximum cores |
|---|---|---|---|---|
| S1012 (9028-21B) | 1 | 4 or 8 | 3.0 ... 3.9 | 8 |
| S1014 (9105-41B) | 1 | 4 or 8 | 3.0 ... 3.9 | 8 |
| S1022s (9105-22B) | 1 or 2 | 4 or 8 | 3.0 ... 4.0 | 16 |
| S1022 (9105-22A) | 1 or 2 | 12, 16 or 20 | 2.45 ... 4.0 | 40 |
| S1024 (9105-42A) | 1 or 2 | 12, 16 or 24 | 2.75 ... 4.0 | 48 |
| E1050 (9043-MRX) | 2 to 4 | 12, 18 or 24 | 2.95 ... 4.0 | 96 |
| E1080 (9080-HEX) | 4 per node, to 4 nodes | 10, 12 or 15 | 3.55 ... 4.15 | 240 |
Clock and core count trade against each other on every Power 10 feature: the smallest core count in a model runs the highest frequency, the largest core count does the most total work at a lower base clock. Exact rated frequency belongs to the specific processor feature code, so confirm it against the feature code rather than the model name before sizing or quoting.
eSCM and DCM: two ways IBM packages the same core
eSCM ... entry single-chip module
One processor chip per module, used on the smaller-core builds. It is the right choice when your core count genuinely stays low, because it delivers better throughput per core than the smallest dual-chip option and keeps the machine in a cheaper software tier.
DCM ... dual-chip module
Two processor chips per module, which is how the S1022, S1024, E1050 and E1080 reach their higher core counts. It is the only way to get real density, but the highest-core features run the lowest base clocks, so it favours consolidation and virtualisation over single-thread response time.
Selected Power 10 models were withdrawn from marketing effective 31 July 2026. That does not affect machines already installed, but it does change how you source a processor upgrade or an MES expansion. Confirm current availability for any specific feature code before you build a plan around adding cores to an existing Power 10.
The processor feature decides your IBM i software tier
The cost that surprises people on Power 10 is not the processor. It is the software tier the processor puts the machine into. IBM i, the licensed program products, and most third-party IBM i software are priced by tier, and that is a recurring cost for the life of the system. Adding cores to fix a capacity problem can quietly move the machine up a tier and cost more every year than the hardware did once.
IBM i software tier by Power 10 model
| Model | IBM i software tier |
|---|---|
| S1012 (9028-21B) | P05 or P10 |
| S1014 (9105-41B) | P05 or P10 |
| S1022s (9105-22B) | P10 |
| S1022 (9105-22A) | P10 |
| S1024 (9105-42A) | P20 or P30 |
| E1050 (9043-MRX) | P20 or P30 planning context |
| E1080 (9080-HEX) | P30 |
The S1024 is where this matters most: the same model sits at P20 or P30 depending on the processor feature, so two machines that look identical on a rack elevation can carry very different annual software bills.
Price the tier before you fix the processor feature. The Power 10 pricing page covers what actually drives cost on this generation, and the Power 10 specs page carries the memory, storage and I/O ceilings that go with each processor choice.
How to read the CPU out of a Power 10 you already run
From IBM i
DSPSYSVAL QPRCFEAT returns the processor feature code. WRKHDWRSC *PRC lists processor resources visible to the partition. Write down QPRCFEAT ... it is the value IBM and every sourcing vendor will ask for.
From AIX, Linux or VIOS
lsconf and prtconf report processor type, implementation and clock speed. lparstat -i gives entitled and online capacity for the partition, which is usually well below what the machine physically holds.
From the HMC
Managed system properties, processor tab. The only place that cleanly separates installed cores from activated cores, which on Power 10 is routinely a large gap because of capacity upgrade on demand.
Before an expansion
For an MES that adds cores, you need the installed module type as well as the activated count, because the module sets the ceiling. A machine with an 8-core eSCM cannot be activated past 8 no matter what the tier allows.
Installed cores, activated cores and licensed cores are three different numbers on Power 10, and quotes are not consistent about which one they mean. Capacity planning uses activated cores, software licensing usually follows activated cores, and upgrade headroom follows installed cores. Get all three in writing.
Upgrade the processor, or move generation
If the CPU is the constraint, the honest comparison is between activating more cores on the machine you have and moving to Power 11. Work it through Power 10 in 2026 and the direct Power 10 vs Power 11 comparison. If you are coming the other way, Power 9 vs Power 10 sets the baseline. Full per-model detail lives in the Power 10 model directory.